1. Field of the Invention
The present invention relates to a communication network and its control method and, more particularly, to a network system which has a node apparatus that can connect a plurality of terminal devices, and parallel multiplex transmission paths for connecting a plurality of node apparatuses.
2. Description of the Related Art
In recent years, as the information volume increases, a network that connects node apparatuses via parallel multiplex transmission paths is being examined to realize a high-speed, large-capacity network which connects terminal devices. For example, examples of the arrangement of such system are described in Japanese Laid-Open Patent Nos. 8-172394 and 8-237306.
In a node apparatus described in Japanese Laid-Open Patent Nos. 8-172394 and 8-237306, one terminal device is connected to each of eight parallel multiplex transmission paths (eight channels), and a packet transmitted from a certain terminal device is output to the channel to which that terminal device is connected in the node apparatus and is then input to an switch fabric of the node apparatus.
The packet is inserted into another channel in the switch fabric, and is then output to a neighboring node apparatus.
The switch fabric used in the node apparatus has eight input terminals and eight output terminals, and sequentially connects these input and output terminals according to specific patterns so as to prevent the input terminals from being connected to a single output terminal in an identical time band, thus switching the channels (see Japanese Laid-Open Patent Nos. 8-172394 and 8-237306 for more).
When communications are made between such node apparatuses, since a terminal device is connected to a given channel, an upstream neighboring node apparatus of the node apparatus to which the destination terminal device of a packet is connected transmits the packet onto the channel to which the destination terminal device is connected.
However, in the above-mentioned prior art, if the destination terminal device of the packet transmitted from a given terminal device is connected to a downstream neighboring node apparatus of the node apparatus to which the source terminal device is connected, the communication band narrows as compared to a case wherein the packet is transmitted to a terminal device connected to another node apparatus.
More specifically, when a packet is transmitted to a terminal device other than that connected to the downstream neighboring node apparatus of the node apparatus to which the source terminal device is connected, the node apparatus to which the source terminal device is connected can transmit that packet using an arbitrary one of a plurality of channels. However, when the packet is transmitted to a terminal device connected to the downstream neighboring node apparatus, the node apparatus must transmit the packet using only the channel to which the destination terminal device is connected.
Hence, in the above-mentioned prior art, communications can be made even when the node apparatus to which the destination terminal device neighbors on the downstream side of the node apparatus to which the source terminal device is connected, but the communication band narrows as compared to a case wherein the node apparatus to which the destination terminal device is connected does not neighbor on the downstream side of the node apparatus to which the source terminal device is connected.
A reference example that partially quotes the arrangement of Japanese Laid-Open Patent No. 8-237306 will be described below to explain the prior art in more detail.
FIG. 5 is a diagram showing the arrangement of a node apparatus in a network of the reference example, and exemplifies an arrangement in which terminals 551 to 558 are connected to a node apparatus 500 via sub transmission paths. Reference numerals 501 to 508 denote separation/insertion units serving as separation/insertion means. Each separation/insertion unit has a function of detecting the addresses of packets input from the corresponding parallel multiplex transmission path, separating them into those to be transmitted to the terminal and those to be input to a buffer, and inserting a packet transmitted from the terminal into a packet flow input form the parallel multiplex transmission path. Reference numerals 511 to 518 denote buffers serving as buffer means each having a function of temporarily storing a packet output from the corresponding separation/insertion unit in a storage area corresponding to the output terminal of a switch 541. Reference numerals 521 to 528 and 531 to 538 denote parallel multiplex transmission paths as a plurality of parallel channels to connect neighboring nodes. These transmission paths are realized by, e.g., a plurality of space division multiplexing optical fiber transmission paths, or wavelength multiplex transmission paths which are wavelength-divided and multiplexed on a single optical fiber. Reference numeral 541 denotes a switch, which is controlled by a switch controller 542 to connect packets input to its input terminals IN1 to IN8 to arbitrary output terminals OUT1 to OUT8. The switch 541 attains switching using a space division switch or the like when a plurality of optical fiber transmission paths are used as the parallel multiplex transmission paths. On the other hand, when wavelength multiplex transmission paths are used, the switch 541 between neighboring nodes is constructed by connecting a transmitter comprising a plurality of variable wavelength laser diodes and a wavelength multiplexer to the wavelength multiplex transmission paths, and separating the respective wavelengths using a wavelength demultiplexer in a receiver of the wavelength multiplex transmission paths, and switches by setting the transmission wavelengths of the variable wavelength laser diodes at arbitrary wavelengths xcex1 to xcex8. Reference numeral 542 denotes a switch controller which controls the switch according to control patterns shown in, e.g., FIG. 4. Reference numeral 543 denotes a buffer controller which controls the buffers to read out the stored packets when the input terminals of the switch connected to the individual buffers are connected to desired output terminals.
FIG. 8 shows the internal arrangement of each of the separation/insertion units 501 to 508. Reference numeral 801 denotes a header detector for detecting the destination address from a packet header; 802 and 803, gates for outputting or intercepting the input signals; 804, a selector for outputting one of the two input signals; and 805, a FIFO (First In First Out) for temporarily storing a packet. In each of the separation/insertion units 501 to 508, the header detector 801 detects the header of a packet input from the corresponding parallel multiplex transmission path, and the gates 802 and 803 are opened/closed depending on the header contents. The header detector 801 pre-stores the address of a terminal connected to that separation/insertion unit, and when the detected destination address matches the stored address, the gates 803 and 802 are respectively opened and closed to output that packet in only the terminal direction. When the detected destination address does not match the stored address, the gates 802 and 803 are respectively opened and closed to output that packet to only the selector, and the packet is sent to the buffer via the selector 804. On the other hand, a packet transmitted from the terminal is temporarily stored in the FIFO 805, and is read out therefrom when the packet flow input from the gate 802 to the selector 804 has a space. Then, the packet is sent to the buffer via the selector 804.
FIG. 3 shows the internal arrangement of each of the buffers 511 to 518. Reference numeral 301 denotes a buffer memory having storage areas 1 to 8 corresponding to the output terminals of the switch 541; 302, a header detector for detecting the destination address from a packet header; and 303, an address counter for supplying a write address to the buffer memory 301. In each of the buffers 511 to 518, a header is detected by the header detector 302 from a packet input from the corresponding separation/insertion unit, and a storage area that stores the packet is determined by the header contents. The header detector 302 pre-stores the addresses of terminals connected to the downstream neighboring node. When the detected destination address matches one of the stored addresses, the header detector 302 designates a storage area corresponding to the transmission path to which the destination terminal is connected, i.e., the output terminal of the switch 541, and makes the address counter 303 generate a write address, thus storing the packet on the buffer memory 301. On the other hand, when the detected destination address matches none of the stored addresses, the header detector 302 controls to store that packet in an arbitrary storage area.
FIG. 4 shows control patterns that represent the input/output connections of the switch 541. The input/output connection of the switch is changed by control addresses A1 to A8. The input terminals IN1 to IN8 respectively correspond to buffers 511 to 518 (input channels 521 to 528), and the output terminals OUT1 to OUT8 (or transmission wavelengths xcex1 to xcex8) respectively correspond to channels 531 to 538.
The switch 541 and buffers 1 to 8 (511 to 518) are synchronously controlled. For example, when buffer 1 is connected to the channel 531, a packet stored in storage area I corresponding to channel 531 is read out from buffer 1. When buffer 1 is connected to the channel 532, a packet stored in a storage area corresponding to the channel 532 is read out from the buffer 1.
FIG. 6 shows an example of the arrangement of a network system using the node apparatuses shown in FIG. 5. Four node apparatuses 601 to 604 are connected in a ring pattern via parallel multiplex transmission paths 605 to 608, and eight terminals are connected to each node apparatus via eight sub transmission paths. Terminals 611 to 618 correspond to the terminals 511 to 558, and similarly, terminals 621 to 628, 631 to 638, and 641 to 648 correspond to the terminals 551 to 558.
FIG. 7 is a diagram for explaining the communication principle of this network. Reference numerals 701 to 704 denote node apparatuses; 705 to 708, switch fabrics corresponding to the switch 541; 709 to 712, buffers corresponding to the buffers 511 to 518; 721 to 736, terminals; and A, B, C, and D, parallel transmission paths that form rings.
The communication principle of this network will be explained below with reference to FIG. 7. This network has a plurality of rings A, B, C, and D, which are connected to each other via the switch fabrics 705 to 708. Each terminal is connected to one of parallel ring transmission paths A, B, C, and D. When a given terminal communicates with a terminal connected to another ring, its output packet is switched at least once to another ring by an arbitrary switch fabric to attain the communication. Although the switching position is not specified, if the packet changes its transmission path to the one connected to the destination node at a node immediately before the destination node, and also changes the transmission path to an arbitrary one in other nodes, communication control is simplified. In this network, in order to simplify the node apparatus, the switch fabrics 705 to 708 repetitively change their input/output connections in accordance with predetermined patterns irrespective of their input signals. The buffers 709 to 712 temporarily store the input signals, and when the input/output connection of the switch fabric is changed to a desired one, a packet is read out from the buffer, thus attaining switching.
For example, when a packet is to be sent from the terminal 722 to the terminal 732, the packet output from the terminal 722 is stored in the buffer 709 of the node 701, and is read out therefrom when the input terminal IN1 of the switch 705 is connected to, e.g., the output terminal OUT2. The readout packet is then output onto the transmission path B, and is input to the buffer 710 of the node 702. When the input terminal IN2 of the switch 706 is connected to the output terminal OUT4, that packet is read out from the buffer, and is output onto the transmission path D. In this way, the packet is sent to the terminal 732.
As described above, a packet communication is done by changing the ring transmission path to an arbitrary one in each node device.
The network system will be explained in detail below with reference to FIGS. 5 and 6. In the following description, the parallel multiplex transmission paths use a plurality of space division multiplexing optical fiber transmission paths, and the switch uses a space division switch. However, the wavelength multiplex transmission paths may also be used based on the above-mentioned principle, and nearly the same operations are made. An example of communications from the terminal 612 to the terminal 635 will be explained.
Transmission data from the terminal 612 is broken up into packets each having a fixed length, and the destination address is added to the header of each packet, thus outputting packets. Each output packet is input to the node apparatus 601 via the sub transmission path, and is temporarily stored in the FIFO 805 of the separation/insertion unit 502. The stored packet is read out from the FIFO 805 when the packet flow input from the gate 802 to the selector 804 has a space, and is then sent to the buffer 512 via the selector 804.
Upon detecting the header of the input packet, the header detector 302 of the buffer 512 determines that a channel need not be designated for that packet, since the detected destination address does not match the stored address and, hence, designates an arbitrary storage area. Upon receiving the information, the write address counter 303 generates a write address, and that packet is written in that storage area of the buffer memory 301. In this case, assume that the packet is stored in storage area 1.
The buffer controller 543 suspends a read of that packet until the input terminal IN2 of the switch 541 is connected to the output terminal OUT1, and reads out the packet when they are connected.
The switch controller 542 sequentially supplies the control address in the order of A1, A2, A3, A4, A5, A6, A7, and A8 as in the table shown in FIG. 4 to change the connection of the switch 541. The switch controller 542 supplies the control address at, e.g., a one-packet-length period, so that identical patterns repetitively appear at eight packet periods. By supplying the information to the buffer controller 543, the read timing from the buffer is controlled. In this case, when the input terminal IN2 of the switch 541 is connected to the output terminal OUT1, the packet is read out from storage area 1 of the buffer 512, and is output onto the transmission path 531 via the switch 541.
The packet sent via the transmission path 531 is input to the separation/insertion unit 501 of the node apparatus 602, and its header is detected by the header detector 802. Since the detected destination address does not match the stored address, the gates 802 and 803 are respectively opened and closed to output that packet to the selector 804. The packet output to the selector 804 in the separation/insertion unit 501 is input to the buffer 511 via the selector 804.
Upon detecting the packet header, the header detector 302 determines that the packet is the one to be output via a designated channel, since the detected destination address matches the stored address, and designates a storage area corresponding to the transmission path to which the terminal indicated by the destination address is connected. In this case, since the destination terminal is connected to the transmission path 535, the packet is stored in storage area 5.
The buffer controller 543 in the node apparatus 602 reads out the packet from storage area 5 of the buffer 511 when the input terminal IN1 of the switch 541 is connected to the output terminal OUT5, thus outputting the packet onto the transmission path 535 via the switch 541. The packet is input to the separation/insertion unit 505 of the node apparatus 603 via the transmission path 535, and its header is detected by the header detector 802. In this case, since the detected destination address matches the stored address, the gates 803 and 802 are respectively opened and closed to output that packet in only the terminal direction. The packet output from the separation/insertion unit 505 in the terminal direction is sent to and received by the terminal 635 via the sub transmission path.
In this way, the communication is done.
When a communication is made toward a terminal connected to the downstream neighboring node apparatus in the network, the communication band narrows as compared to a communication to a terminal connected to the node apparatus other than the downstream neighboring node apparatus. This problem will be explained in detail below.
A procedure for transmitting a packet to a terminal connected to the downstream neighboring node will be explained below with reference to FIGS. 5 and 6. In the following description, the parallel multiplex transmission paths use a plurality of space division multiplexing optical fiber transmission paths, and the switch uses a space division switch. However, the wavelength multiplex transmission paths may also be used based on the above-mentioned principle, and nearly the same operations are made. An example of communications from the terminal 612 to the terminal 625 will be explained.
Transmission data from the terminal 612 is broken up into packets each having a fixed length, and the destination address is added to the header of each packet, thus outputting packets. Each output packet is input to the node apparatus 601 via the sub transmission path, and is temporarily stored in the FIFO 805 of the separation/insertion unit 502. The stored packet is read out from the FIFO 805 when the packet flow input from the gate 802 to the selector 804 has a space, and is then sent to the buffer via the selector 804.
Upon detecting the header of the input packet, the header detector 302 of the buffer 512 designates a storage area corresponding to the transmission path to which the terminal indicated by the destination address is connected, since the detected destination address matches the stored address. In this case, since the destination terminal is connected to the transmission path 535, the packet is stored in storage area 5.
The switch controller 542 sequentially supplies the control address in the order of A1, A2, A3, A4, A5, A6, A7, and A8 as in the table shown in FIG. 4 to change the connection of the switch 541. Also, the switch controller 542 supplies the control address at, e.g., a one-packet-length period, so that identical patterns repetitively appear at eight packet periods. By supplying the information to the buffer controller 543, the read timing from the buffer is controlled.
When the input terminal IN2 of the switch 541 is connected to the output terminal OUT5, the buffer controller 543 reads out the packet from storage area 5 of the buffer 512, thus outputting the packet onto the transmission path 535 via the switch 541. The packet is input to the separation/insertion unit 505 of the node apparatus 602 via the transmission path, and its header is detected by the header detector 802. In this case, since the detected destination address matches the stored address, the gates 803 and 802 are respectively opened and closed to output that packet in only the terminal direction. The packet output from the separation/insertion unit 505 in the terminal direction is sent to and received by the terminal 625 via the sub transmission path.
In this fashion, the communication from the terminal 612 to the terminal 625 is made.
However, in this procedure, the communication band narrows as compared to a communication between non-neighboring node apparatuses, as will be described below.
The communication band between non-neighboring node apparatuses will be calculated first. Assume that the transmission band per transmission path and that of the sub transmission path between each terminal and node apparatus are respectively T bps. In case of the above reference example, i.e., the communication from the terminal 612 to the terminal 635, the communication band is calculated as follows:
1. The communication rate from the terminal 612 to the node apparatus 601 is T bps.
2. The communication rate from the separation/insertion unit 502 to the buffer 512 is T bps.
3. Since packets are written in arbitrary storage areas in the buffer 512, and storage areas 1 to 8 are read out in turn by the buffer controller 543, the communication rate from the buffer 512 to the switch 541 is T bps and, hence, that of the output from the switch 541 is also T bps (as a total of the eight transmission paths).
4. The communication rate from the node apparatus 601 to the node apparatus 602 is T bps (as a total of the eight transmission paths).
5. The communication rate between the separation/insertion units 501 to 508 and buffers 511 to 518 in the node apparatus 602 is T bps (as a total of the eight transmission paths).
6. Since the packets are written in storage areas 5 in buffers 511 to 518, and these storage areas 5 are read out at different timings, the communication rate from the buffers 511 to 518 to the switch 541 is T bps.
7. Since the packets are read out and input to the switch 541 via the input terminals IN1 to IN8 and are switched to the output terminal OUT5 at different timings, the communication rate is T bps and, hence, that of the output from the switch 541 is T bps (the transmission path 535 alone).
8. The communication rate from the node apparatus 602 to the node apparatus 603 is T bps (single transmission path).
9. The communication rate from the separation/insertion unit 505 in the node apparatus 603 to the terminal 635 is T bps.
Hence, since the communication rate throughout the communication path is T bps, the communication band of the communication from the terminal 612 to the terminal 635 is T bps.
By contrast, the communication band of the communication from the terminal 612 to the terminal 625 is calculated as follows:
1. The communication rate from the terminal 612 to the node apparatus 601 is T bps.
2. The communication rate from the separation/insertion unit 502 to the buffer 512 is T bps.
3. Since packets are written in storage area 5 in the buffer 512, and storage area 5 is read out by the buffer controller 543 at a timing once per eight packet periods, the communication rate from the buffer 512 to the switch 541 is T/8 bps. Hence, the communication rate of the output from the switch 541 is also T/8 bps.
4. The communication rate from the node apparatus 601 to the node apparatus 602 is T bps (single transmission path).
5. The communication rate from the separation/insertion unit 505 of the node apparatus 602 to the terminal 625 is T bps.
Hence, the rate of 3. becomes a bottleneck (T/8 bps), and the communication band of the communication from the terminal 612 to the terminal 625 becomes T/8 bps.
It is an object of the present invention to prevent the communication band from narrowing even when the destination terminal of a packet transmitted from a given terminal device is connected to the downstream neighboring node apparatus of the node apparatus to which the source terminal device of that packet is connected.
It is another object of the present invention to prevent the communication band from narrowing even when the destination terminal of a packet transmitted from a terminal device connected to a node apparatus, which switches packets by connecting a plurality of input terminals and a plurality of output terminals in accordance with predetermined patterns that can prevent a plurality of input terminals from being simultaneously connected to a single output terminal, is connected to the downstream neighboring node apparatus of that node apparatus.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.